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27MHz Multiple output XO with Audio Clock
https://abracon.com/SiOsc/ABM0122.pdf
27MHz Multiple output XO with Audio Clock 30332 Esperanza., Rancho Santa Margarita, Ca 92688 Ph: 949-546-8000 Fax: 949-546-8001 www.Abracon.com 03/21/05 Page 1 FEATURES • 2 XO outputs at 27MHz (27MHz crystal input). • Selectable Audio Clocks supporting: 232kHz, 44.1kHz, 48kHz, 64kHz and 96kHz sampling rates
27MHz XO IC with Audio Clock (for Set Top Boxes & MPEG …
https://abracon.com/SiOsc/ABMX0127.pdf
24.576MHz audio frequencies • On-the-fly switching of the audio frequency. • 01273.3V Operating Voltage. • Available in 8-Pin SOIC. DESCRIPTION The ABMX0127 is a low cost integrated XO IC designed to work with a fundamental 27MHz crystal or a clock input. In addition to a 27MHz clock reference, it provides the most common audio clocks
MAX9485 Programmable Audio Clock Generator - Maxim …
https://www.maximintegrated.com/en/products/all-products/archive/MAX9485.html
The MAX9485 programmable multiple-output clock generator provides a cost-efficient solution for MPEG-2 audio systems such as DVD players, DVD drives for multimedia PCs, digital HDTV systems, home entertainment centers, and set-top boxes. The MAX9485 accepts an input reference frequency of 27MHz from a crystal or system reference clock.
PCM1863 with 27MHz clock PLL divider settings? - Audio ...
https://e2e.ti.com/support/audio/f/6/t/415473?PCM1863-with-27MHz-clock-PLL-divider-settings-
I clock the PCM1863 on the SCKI pin with 27.000MHz. Using the formula from chapter 8.13.5 I calculate my PLL settings: PLLCKIN is 27MHZ (video clock) PLLCK selected to be 98.304MHz. PLLCK = (PLLCKIN*R*K) / P. values calculated: P=2, R=1, K=7.2818. K …
High Pull-Range VCXO (27MHz) with integrated Audio PLL
http://datasheet.digchip.com/634/634-00070-0-PLL502-26.pdf
OUT_Audio 11 O Audio clock output. VDD_Audio 12 P +3.3V VDD power supply pin for Audio clock output buffer. This pin should be decoupled separately from other VDD. VDD_27MHz 13 P +3.3V VDD po wer supply pin for 27MHz output clock. This pin should be decoupled separately from other VDD. OUT_27MHz 14 O 27MHz VCXO output clock. GND_27MHz 15 P GND ...
VCXO PLUS AUDIO CLOCK FOR STB MK3722
https://www.renesas.com/us/en/document/dst/mk3722-datasheet
VCXO PLUS AUDIO CLOCK FOR STB MK3722 IDT™ VCXO PLUS AUDIO CLOCK FOR STB 1 MK3722 REV G 051310 Description The MK3722 is a low cost, low jitter, high performance ... 12 27M Output 27MHz reference clock output. 13 S0 Input Select input S0. Selects ACLK per table above. Internal pull-up. 14 VDD Power Connect to +3.3V.
US6151479A - Single clock 27 MHZ oscillator in MPEG-2 ...
https://patents.google.com/patent/US6151479A/en
The desired audio clock frequency is generated from the same fixed 27 MHZ clock used to generate the video, CPU, and modem clocks. As shown in FIG. 3, the 27 MHZ crystal 11 provides a 27 MHZ +/-25 ppm frequency to Divider A 24, which divides the 27 MHZ signal by either 1125 or 1875 thereby creating either a 24 KHz or a 14.4 KHz first reference ...
EVALUATION KIT Programmable Audio Clock Generator
https://pdfserv.maximintegrated.com/en/ds/MAX9485.pdf
♦ 27MHz Crystal with ±30ppm Frequency Reference ♦ Two Buffered Output Ports with Multiple Audio Clocks: 256, 384, or 768 Times fS ♦ Supports Standard and Double Sampling Rates (12kHz, 32kHz, 44.1kHz, 48kHz, 64kHz, 88.2 kHz, and 96kHz) ♦ I2C Interface or Hardwired Output Clock Selection ♦ Separate Output Clock Enable
PLL1700 data sheet, product information and support | TI.com
https://www.ti.com/product/PLL1700
The PLL1700 can generate four systems clocks from a 27MHz reference input frequency. The device gives customers both cost and space savings by eliminating external components and enables customers to achive the very low jitter performance needed for high performance audio digital-to-analog converters (DAC) and/or analog-to-digital converters (ADC).
TIDA-00424 reference design | TI.com
https://www.ti.com/tool/TIDA-00424
Features Sync separation from incoming video signal Precision clock generation synchronous to the incoming video signal Multiple PLL's to generate video clocks at 27MHz, 148.5MHz, 148.35MHz, and audio clock at 24.576MHz Clock distribution with output drivers Self-contained video clock sub-system Proven design with demo board, design files and GUI
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