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UDA1334ATS Low power audio DAC with PLL - NXP
https://www.nxp.com/docs/en/data-sheet/UDA1334ATS.pdf
This audio DAC is excellently suitable for digital audio portable application, specially in applications in which an audio related system clock is not present. 3 GENERAL DESCRIPTION The UDA1334ATS is a single chip 2 channel digital-to-analog converter employing bitstream conversion techniques, including an on-board PLL.
Audio PLL
https://onlinedocs.microchip.com/pr/GUID-5474CCCD-F385-4AD7-9759-539BB1019357-en-US-5/GUID-86B2373A-36A3-4642-B124-B9574596EE6F.html
The Audio PLL is a high-resolution fractional-N digital PLL specifically designed for low jitter operation. In audio applications, the CLK_AUDIO output pin typically serves as the Master clock frequency generator for external components such as Audio DAC, Audio ADCs, or Audio Codecs, thus saving one crystal on the board.. The reference clock of the Audio PLL is the fast crystal …
8-Channel DAC with PLL and Single-Ended Outputs, …
https://www.analog.com/media/en/technical-documentation/data-sheets/AD1934.pdf
PLL generated or direct master clock Low EMI design . 108 dB DAC dynamic ran ge and SNR . −94 dB THD + N . Single 3.3 V supply . Tolerance for 5 V logic inputs . Supports 24 bits and 8 kHz to 192 kHz sample rates . Single-ended DAC output . Log volume control with auto ramp function . SPI® controllable for flexibility . Software-controllable ...
audio pll IP core / Semiconductor IP / Silicon IP
https://www.design-reuse.com/sip/?q=audio+pll&
95 dB of SNR, Pure logic stereo audio DAC with patented PLL-less feature 5. The CODEC integrates: 2-channel 24-bit sigma-delta ADC, 2-channel 24-bit sigma-delta DAC with headphone driver amplifier, and audio PLL to support a wide range of sample rates. The S13V33_CODEC_04 integrates: 2-channel 24bit sigma-delta ADC, 2-channel 24bit sigma-delta ...
2 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec
https://www.analog.com/media/en/technical-documentation/data-sheets/ADAU1328.pdf
digital audio input/output precision voltage reference timing management and control (clock and pll) control port spi control data input/output 12.488mhz 6.144mhz adau1328 adc adc dac dac dac dac dac dac dac dac digital filter and volume control sdata …
MAX9850 Stereo Audio DAC with DirectDrive® …
https://www.maximintegrated.com/en/products/analog/audio/MAX9850.html
The audio DAC receives input data over a flexible 3-wire interface that supports left-justified, right-justified audio data, or I²S-compatible audio data. Stereo audio line inputs are provided to either mix analog audio with the digital input stream, or to drive the headphone outputs directly.
HoloAudio – May DAC | Kitsune HiFi - HoloAudio USA
https://www.kitsunehifi.com/product/holo-audio-may-dac/
Specs and General info: Dimensions per chassis (2 total): 430 mm (W) * 300 mm (L) * 55 mm (H) additional 12 mm for machined feet (for each part, two of these chassis stacked on each other) Weight: 18.0 kg Approximately for both Chassis or about 39.68Lbs Power Consumption: 60W Accessories included: power cord (NorthAmerica ONLY), remote control, DC Power Cable (1M …
Analyzing Audio DAC Jitter Sensitivity | Maxim Integrated
https://www.maximintegrated.com/en/design/technical-documents/app-notes/5/5477.html
The cycle-skipped clock used for this study is shown in Figure 5 and the jitter spectrum of this clock is illustrated in Figure 6 and Figure 7.This cycle-skipped clock test demonstrates that a very easily generated, extremely jittery …
Ultra Low Power Stereo Audio Codec With Integrated ...
https://www.ti.com/lit/ds/slos756/slos756.pdf
2• Stereo Audio DAC with 100dB SNR • Mobile Handsets • 4.1mW Stereo 48ksps Playback • Communication • PowerTune™ • Portable Computing ... BCLK, GPIO pins or the output of internal PLL, where the input to the PLL again can be derived from the MCLK, BCLK or GPIO pins. Although using the internal, fractional PLL ensures the ...
JacobsPineda.com
https://www.jacobspineda.com/
The JDA1 is core cell design for a high-performance delta-sigma audio D/A converter (DAC) with an integral Phase Lock Loop (PLL) that can be manufactured using off-the-shelf digital processes with off-the-shelf gate array or standard cell libraries. The JDA1 is exceptionally efficient, and requires only 0.3 - 0.4 sqmm of silicon area (based on data from several standard 3LM 0.18u …
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