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AES E-Library » Hardware/Software Co-Design of Multi ...
https://www.aes.org/e-lib/browse.cfm?elib=14479
abstract={this paper presents a hardware/software co-design method for the implementation of multi-format audio decoder with ultra low power, small chip size, and high flexibility which are most critical factors in embedded devices. this approach can provide both flexibility and low power with high performance in such a way that hardware implementation …
A Hardware/Software Co-Design of MP3 Audio Decoder ...
https://www.researchgate.net/publication/220540478_A_HardwareSoftware_Co-Design_of_MP3_Audio_Decoder
Audio applications for mobile phone and portable devices are increasingly popular. To attract consumer interest, a multi-standard design on a single …
(PDF) An SoC based HW/SW co-design architecture for …
https://www.researchgate.net/publication/4308434_An_SoC_based_HWSW_co-design_architecture_for_multi-standard_audio_decoding
This paper presents a hardware/software co-design method for the implementation of multi-format audio decoder with ultra low power, small chip size, and high flexibility which are …
A Hardware/Software Co-design of High Efficiency AAC …
https://link.springer.com/article/10.1007%2Fs11265-016-1165-y
This paper presents an implementation of hardware/software co-design for high efficiency advanced-audio-coding (HE-AAC) audio decoder. The decoder system is partitioned into software and hardware part throughout the computation analysis. In our design strategy, the bitstream parser and lower complexity part are performed by software solution, and the higher …
Specification and Design of a MP3 Audio Decoder
http://www.cecs.uci.edu/~doemer/publications/CECS_TR_05_04.pdf
In this report, we describe the system level design process adopted to design a MP3 Audio decoder. We adopted the SpecC design methodology and developed a specication model of a MP3 audio decoder in SpecC language and used the System On a Chip Environment (SCE) developed at Cen-
Hardware/Software Co-reconfigurable Instruction Decoder ...
https://link.springer.com/article/10.1007/s11265-010-0461-1
The programmable instruction decoder (PID) architecture developed in a hardware/software co-reconfigurable approach for multi-core DSP systems was described. PID hardware can be implemented as a fast, risk-sensitive ASIC with adequate flexibility for future seamless software upgrade and migration toward other greater number of DSP-cores in a chip …
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