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I2S Audio Interface - Silvaco
https://silvaco.com/wp-content/uploads/product/ip/pdf/70027_I2S_Brief.pdf
The I2S bus interface of the I2S Audio Interface is a set of unidirectional signals that connect to chip I/O pads to form the off-chip I2S bus signals: serial clock (I2SCLK), word select (I2SWS), serial data in (I2SSDI), and serial data out (I2SSDO). To reduce chip-level pin count, the I2S bus interface signals can be shared with other on-chip
audio - How to decide about master or slave mode in I²S ...
https://electronics.stackexchange.com/questions/273066/how-to-decide-about-master-or-slave-mode-in-i%C2%B2s-i2s
Note: Of course, ADC/DAC/SoC are not the only kind of devices you can find in a I2S system. But for the other kind of devices, the same rationale can often be applied. For example: S/PDIF transmitters are often slave-only, while receivers can usually act as both master or slave.
I2S Multi-Slave / Multi-Master configurations - Audio ...
https://e2e.ti.com/support/audio-group/audio/f/audio-forum/426477/i2s-multi-slave-multi-master-configurations
Hi _Lina, I suggest to take a look of this document: Audio Serial Interface Configurations for Audio Codecs.It could help you to understand about the I2S behavior as a master and as a slave. Regarding your question about the communication between slaves, when a device is working as slave, the BCLK and WCLK are placed as inputs.
I2S — Inter-IC sound interface - Nordic Semiconductor
https://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52832.ps.v1.1/i2s.html
I 2 S — Inter-IC sound interface The I 2 S (Inter-IC Sound) module, supports the original two-channel I 2 S format, and left or right-aligned formats. It implements EasyDMA for sample transfer directly to and from RAM without CPU intervention. The I 2 S peripheral has the following main features: Master and Slave mode
Using the I2S Audio Interface of DS90Ux92x FPD-Link …
https://www.ti.com/lit/an/snla221/snla221.pdf
clocking signals to act as I2S slave and the Deserializer device regenerates all of the necessary clocking signals to act as I2S master. Table 2 below covers the range of I2S sample rates, most common word sizes and bit rate combinations. 2 Using the I2S Audio Interface of DS90Ux92x FPD-LinkIII Devices SNLA221– June 2013 Submit Documentation Feedback
I2S bus specification - SparkFun Electronics
https://www.sparkfun.com/datasheets/BreakoutBoards/I2SBUS.pdf
In the I2S format, any device can act as the system master by providing the necessary clock signals. A slave will usually derive its internal clock signal from an external clock input. This means, taking into account the propagation delays between master clock and the data and/or word-select signals, that the total delay is simply the sum of:
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